View DS3050W_270094.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Rev 0; 4/05
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock
General Description
The DS3050W consists of a static RAM, a nonvolatile (NV) controller, a year 2000-compliant real-time clock (RTC), and an internal rechargeable manganese lithium (ML) battery. These components are encased in a surface-mount module with a 256-ball BGA footprint. Whenever VCC is applied to the module, it recharges the ML battery, powers the clock and SRAM from the external power source, and allows the contents of the clock registers or SRAM to be modified. When VCC is powered down or out-of-tolerance, the controller writeprotects the memory contents and powers the clock and SRAM from the battery. The DS3050W also contains a power-supply monitor output (RST), as well as a user-programmable interrupt output (IRQ/FT).
Features
Single-Piece, Reflowable, 27mm x 27mm BGA Package Footprint Internal Manganese Lithium Battery and Charger Integrated Real-Time Clock Unconditionally Write-Protects the Clock and SRAM when VCC is Out-of-Tolerance Automatically Switches to Battery Supply when VCC Power Failures Occur Reset Output can be Used as a CPU Supervisor Interrupt Output can be Used as a CPU Watchdog Timer Industrial Temperature Range (-40C to + 85C) UL Recognized
DS3050W
Applications
RAID Systems and Servers POS Terminals Industrial Controllers Data-Acquisition Systems Gaming Fire Alarms PLCs Routers/Switches
Ordering Information
PART DS3050W-100 TEMP RANGE -40C to +85C PIN-PACKAGE 256-ball 27mm x 27mm BGA Module SPEED 100ns SUPPLY VOLTAGE (%) 3.3V 0.3V
Typical Operating Circuit
CE WR RD CS CE WE OE CS
MICROPROCESSOR OR DSP DATA
DS3050W
8 BITS DQ0-7
512k x 8 NV SRAM AND RTC
ADDRESS
19 BITS
A0-18
INT INT
IRQ/FT RST
Pin Configuration appears at end of data sheet. ______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock DS3050W
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground......-0.3V to +4.6V Operating Temperature Range ...........................-40C to +85C Storage Temperature Range ...............................-40C to +85C Soldering Temperature Range .......See IPC/JEDEC J-STD-020C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +85C.)
PARAMETER Supply Voltage Input Logic 1 Input Logic 0 SYMBOL VCC VIH VIL CONDITIONS MIN 3.0 2.2 0.0 TYP 3.3 MAX 3.6 VCC 0.4 UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V 0.3V, TA = -40C to +85C.)
PARAMETER Input Leakage Current I/O Leakage Current Output-Current High Output-Current Low Output-Current Low RST Output-Current Low IRQ/FT Standby Current Operating Current Write Protection Voltage SYMBOL IIL IIO IOH IOL IOL RST ICCS1 ICCS2 ICCO1 VTP CE = CS = VCC At 2.4V At 0.4V At 0.4V (Note 1) CE = CS = 2.2V CE = CS = VCC - 0.2V tRC = 200ns, outputs open 2.8 2.9 CONDITIONS MIN -1.0 -1.0 -1.0 2.0 8.0 7.0 0.5 0.2 7 5 50 3.0 TYP MAX +1.0 +1.0 UNITS A A mA mA mA mA mA mA V
IOL IRQ/FT At 0.4V (Note 1)
PIN CAPACITANCE
(TA = +25C.)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN COUT CONDITIONS Not production tested Not production tested MIN TYP 15 15 MAX UNITS pF pF
2
_____________________________________________________________________
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V 0.3V, TA = -40C to +85C.)
PARAMETER Read Cycle Time Access Time OE to Output Valid RTC OE to Output Valid CE or CS to Output Valid OE or CE or CS to Output Active Output High Impedance from Deselection Output Hold from Address Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Impedance from WE Output Active from WE Data Setup Time Data Hold Time Chip-to-Chip Setup Time SYMBOL tRC tACC tOE tOEC tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2 tCCS (Note 4) (Note 5) (Note 2) (Note 2) (Note 6) (Note 4) (Note 5) 5 40 0 20 40 (Note 3) (Note 2) (Note 2) 5 100 75 0 5 20 40 5 40 CONDITIONS DS3050W-100 MIN 100 100 50 60 100 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DS3050W
POWER-DOWN/POWER-UP TIMING
(TA = -40C to +85C.)
PARAMETER VCC Fail Detect to CE, CS, and WE Inactive VCC Slew from VTP to 0V VCC Slew from 0V to VTP VCC Valid to CE, CS, and WE Inactive VCC Valid to End of Write Protection VCC Fail Detect to RST Active VCC Valid to RST Inactive SYMBOL tPD tF tR tPU tREC tRPD tRPU (Note 1) (Note 1) 40 350 (Note 7) 150 150 2 125 3.0 525 CONDITIONS MIN TYP MAX 1.5 UNITS s s s ms ms s ms
_____________________________________________________________________
3
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock DS3050W
DATA RETENTION
(TA = +25C.)
PARAMETER Expected Data-Retention Time (Per Charge) SYMBOL tDR (Notes 7, 8) CONDITIONS MIN 2 TYP 3 MAX UNITS Years
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
Note 9: Note 10: Note 11: Note 12: Note 13:
IRQ/FT and RST are open-drain outputs and cannot source current. External pullup resistors should be connected to these pins to realize a logic-high level. These parameters are sampled with a 5pF load and are not 100% tested. tWP is specified as the logical AND of CE with WE for SRAM writes, or CS with WE for RTC writes. tWP is measured from the latter of the two related edges going low to the earlier of the two related edges going high. tWR1 and tDH1 are measured from WE going high. tWR2 and tDH2 are measured from CE going high for SRAM writes or CS going high for RTC writes. tDS is measured from the earlier of CE or WE going high for SRAM writes, or from the earlier of CS or WE going high for RTC writes. In a power-down condition, the voltage on any pin may not exceed the voltage on VCC. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. Minimum expected data-retention time is based upon a maximum of two +230C convection reflow exposures, followed by a fully charged cell. Full charge occurs with the initial application of VCC for a minimum of 96 hours. This parameter is assured by component selection, process control, and design. It is not measured directly during production testing. WE is high for any read cycle. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. If the CE or CS low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high-impedance state during this period. If the CE or CS high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-impedance state during this period. If WE is low or the WE low transition occurs prior to or simultaneously with the related CE or CS low transition, the output buffers remain in a high-impedance state during this period.
4
_____________________________________________________________________
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock
Read Cycle
DS3050W
tRC VIH VIL VIH VIL tOH tACC CE OR CS VIH VIL tCO tOEC tOE VIL tCOE tCOE DOUT VOH VOL OUTPUT DATA VALID tOD VOH VOL VIH VIH VIL
ADDRESSES
tOD VIH
VIH OE
(SEE NOTE 9.)
_____________________________________________________________________
5
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock DS3050W
Write Cycle 1
tWC ADDRESSES VIH VIL tAW CE OR CS WE VIH tODW DOUT HIGH IMPEDANCE tDS VIH DIN VIL (SEE NOTES 2, 3, 4, 6, 10-13.) DATA IN STABLE VIL tDH1 VIH VIL tWP VIL VIL VIH tOEW VIL tWR1 VIH VIL VIH VIL
Write Cycle 2
tWC
ADDRESSES
VIH VIL tAW tWP VIH VIL VIL VIL VIH tWR2
VIH VIL
VIH VIL
CE OR CS
VIH
WE tCOE
VIL tODW
VIL
DOUT tDS VIH DIN VIL (SEE NOTES 2, 3, 5, 6, 10-13.) DATA IN STABLE VIL tDH2 VIH
6
_____________________________________________________________________
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock
Power-Down/Power-Up Condition
VCC VTP tDR
DS3050W
~2.5V
tF tPD CE, WE AND CS BACKUP CURRENT SUPPLIED FROM LITHIUM BATTERY tRPD RST VOL VOL tRPU tPU VIH tR tREC SLEWS WITH VCC
(SEE NOTES 1, 7.)
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. OPERATING FREQUENCY
DS3050W toc01
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS3050W toc02
BATTERY CHARGER CURRENT vs. BATTERY VOLTAGE
BATTERY CHARGER CURRENT, ICHARGE (mA) VCC = CE = 3.3V 7 6 5 4 3 2 1 0 0 VCHARGE = 2.86V 0.2 0.4 0.6 0.8 1.0
DS3050W toc03
7 TA = +25C 6 SUPPLY CURRENT (mA) 5 4 3 2 1 0 3.0 3.1 3.2 3.3 VCC (V) 3.4 3.5 5MHz ADDRESS-ACTIVATED 100% DUTY CYCLE 1MHz CE-ACTIVATED 50% DUTY CYCLE 5MHz CE-ACTIVATED 50% DUTY CYCLE
1000 VCC = CE = 3.3V, VBAT = VCHARGE, OSC = ON
8
900 SUPPLY CURRENT (A)
800
700
600 1MHz ADDRESS-ACTIVATED 100% DUTY CYCLE 500 3.6 3.0 3.1 3.2 3.3 VCC (V) 3.4 3.5 3.6
DELTA V BELOW VCHARGE (V)
_____________________________________________________________________
7
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock DS3050W
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
VCHARGE PERCENT CHANGE vs. TEMPERATURE
DS3050W toc04
WRITE PROTECTION VOLTAGE vs. TEMPERATURE
DS3050W toc05
DQ OUTPUT-VOLTAGE HIGH vs. DQ OUTPUT-CURRENT HIGH
VCC = 3.3V 3.3
DS3050W toc06
1.0 VCHARGE PERCENT CHANGE FROM 25C (%) VCC = 3.3V, VBAT = VCHARGE 0.5
3.00
3.5
WRITE PROTECT, VTP (V)
2.95 VOH (V) -40 85
3.1
0
2.90
2.9 2.85
-0.5
2.7
-1.0 -40 -15 10 35 60 85 TEMPERATURE (C)
2.80 -15 10 35 60 TEMPERATURE (C)
2.5 -5 -4 -3 -2 -1 0 IOH (mA)
DQ OUTPUT-VOLTAGE LOW vs. DQ OUTPUT-CURRENT LOW
DS3050W toc07
IRQ/FT OUTPUT-VOLTAGE LOW vs. OUTPUT-CURRENT LOW
DS3050W toc08
4 VCC = 3.3V 3
6 5 4
VOL (V)
2
VOL (V) 0 1 2 IOL (mA) 3 4 5
3 2
1 1 0 0 0 5 10 IOL (mA) 15 20
RST OUTPUT-VOLTAGE LOW vs. OUTPUT-CURRENT LOW
DS3050W toc09
RST VOLTAGE vs. VCC DURING POWER-UP
RST VOLTAGE W/PULLUP RESISTOR (V) TA = +25C 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
DS3050W toc10
6 5 4 VOL (V) 3 2 1 0 0 5 10 IOL (mA) 15
4.0
20
VCC POWER-UP (V)
8
_____________________________________________________________________
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock
Pin Description
BALLS A1, A2, A3, A4 B1, B2, B3, B4 C1, C2, C3, C4 D1, D2, D3, D4 E1, E2, E3, E4 F1, F2, F3, F4 G1, G2, G3, G4 H1, H2, H3, H4 J1, J2, J3, J4 K1, K2, K3, K4 L1, L2, L3, L4 M1, M2, M3, M4 N1, N2, N3, N4 P1, P2, P3, P4 R1, R2, R3, R4 T1, T2, T3, T4 U1, U2, U3, U4 V1, V2, V3, V4 W1, W2, W3, W4 Y1, Y2, Y3, Y4 A17, A18, A19, A20 B17, B18, B19, B20 C17,C18,C19, C20 D17, D18, D19, D20 E17, E18, E19, E20 F17, F18, F19, F20 G17, G18, G19, G20 H17, H18, H19, H20 J17, J18, J19, J20 K17, K18, K19, K20 L17, L18, L19, L20 M17, M18, M19, M20 NAME GND DESCRIPTION Ground BALLS N17, N18, N19, N20 P17, P18, P19, P20 R17, R18, R19, R20 T17, T18, T19, T20 U17, U18, U19, U20 V17, V18, V19, V20 W17, W18, W19, W20 Y17, Y18, Y19, Y20 A5, B5, C5, D5 A6, B6, C6, D6 A7, B7, C7, D7 A8, B8, C8, D8 A9, B9, C9, D9 A10, B10, C10, D10 A11, B11, C11, D11 A12, B12, C12, D12 A13, B13, C13, D13 A14, B14, C14, D14 A15, B15, C15, D15 A16, B16, C16, D16 U5, V5, W5, Y5 U6, V6, W6, Y6 U7, V7, W7, Y7 U8, V8, W8, Y8 U9, V9, W9, Y9 U10, V10, W10, Y10 U11, V11, W11, Y11 U12, V12, W12, Y12 U13, V13, W13, Y13 U14, V14, W14, Y14 U15, V15, W15, Y15 U16, V16, W16, Y16 NAME A5 A4 A3 A2 A1 A0 GND GND N.C. N.C. N.C. N.C. N.C. VCC N.C. N.C. N.C. N.C. N.C. N.C. CS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. DESCRIPTION Address Input 5 Address Input 4 Address Input 3 Address Input 2 Address Input 1 Address Input 0 Ground Ground No Connection No Connection No Connection No Connection No Connection Supply Voltage No Connection No Connection No Connection No Connection No Connection No Connection RTC Chip Select No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection
DS3050W
Interrupt/Frequency Test IRQ/FT Output A15 A16 RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND GND GND GND A18 A17 A14 A13 A12 A11 A10 A9 A8 A7 A6 Address Input 15 Address Input 16 Reset Output Supply Voltage Write Enable Input Output Enable Input SRAM Chip Enable Input Data Input/Output 7 Data Input/Output 6 Data Input/Output 5 Data Input/Output 4 Data Input/Output 3 Data Input/Output 2 Data Input/Output 1 Data Input/Output 0 Ground Ground Ground Ground Address Input 18 Address Input 17 Address Input 14 Address Input 13 Address Input 12 Address Input 11 Address Input 10 Address Input 9 Address Input 8 Address Input 7 Address Input 6
_____________________________________________________________________
9
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock DS3050W
Functional Diagram
32.768kHz
IRQ/FT
CS
CS A0-A3 WE OE REAL-TIME CLOCK
RST
CE DELAY TIMING CIRCUITRY
VTP REF
CHARGER CURRENT-LIMITING RESISTOR
UNINTERRUPTED POWER SUPPLY FOR THE SRAM AND RTC
VCC
VCC CE VSW REF OE WE SRAM DQ0-7
REDUNDANT LOGIC
ML GND
CURRENT-LIMITING RESISTOR
REDUNDANT SERIES FET
BATTERY-CHARGING/SHORTING PROTECTION CIRCUITRY (U.L. RECOGNIZED)
OE WE A0-A18
DS3050W
10
____________________________________________________________________
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock DS3050W
Detailed Description
The DS3050W is a 4Mb (512k x 8 bits) fully static, NV memory similar in function and organization to the DS1250W NV SRAM, but also containing an RTC and rechargeable ML battery. The DS3050W NV SRAM constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. There is no limit to the number of write cycles that can be executed, and no additional support circuitry is required for microprocessor interfacing. This device can be used in place of SRAM, EEPROM, or flash components. User access to either the SRAM or the real-time clock registers is accomplished with a byte-wide interface and discrete control inputs, allowing for a direct interface to many 3.3V microprocessor devices. The DS3050W RTC contains a full-function, year 2000compliant (Y2KC) clock/calendar with an RTC alarm, watchdog timer, battery monitor, and power monitor. RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in a 24-hour BCD format. Corrections for day of the month and leap year are made automatically. The DS3050W RTC registers are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. Assuming the internal oscillator is on, the internal registers are continually updated, regardless of the state of the external registers, assuring that accurate RTC information is always maintained. The DS3050W contains interrupt (IRQ/FT) and reset (RST) outputs, which can be used to control CPU activity. The IRQ/FT interrupt output can be used to generate an external interrupt when the RTC register values match user-programmed alarm values. The interrupt is always available while the device is powered from the system supply, and it can be programmed to occur when in the battery-backed state to serve as a system wake-up. The IRQ/FT output can also be used as a CPU watchdog timer. CPU activity is monitored and an interrupt can be activated if the correct activity is not detected. The RST output can be used to detect a system power-down or failure and hold the CPU in a safe state until normal power returns. The DS3050W constantly monitors the voltage of the internal battery. The battery-low flag (BLF) in the RTC FLAGS register is not writeable and should always be a 0 when read. Should a 1 ever be present, the battery voltage is below 2V and the contents of the clock and SRAM are questionable. The DS3050W module is constructed on a standard 256ball, 27mm x 27mm BGA substrate. Unlike other surface-mount NV memory modules that require the battery to be removable for soldering, the internal ML battery can tolerate exposure to convection reflow soldering temperatures, allowing this single-piece component to be handled with standard BGA assembly techniques.
Table 1. RTC/Memory Operational Truth Table
CS 0 0 0 1 1 1 1 0 WE 1 1 0 1 1 0 X X CE 1 1 1 0 0 0 1 0 OE 0 1 X 0 1 X X X MODE RTC Read RTC Read RTC Write SRAM Read SRAM Read SRAM Write Standby Invalid (1) ICC Active Active Active Active Active Active Standby Active OUTPUTS Active High Impedance High Impedance Active High Impedance High Impedance High Impedance Invalid
X = Don't care. (1) = See Figure 4.
____________________________________________________________________
11
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock DS3050W
SRAM Read Mode
The DS3050W executes an SRAM read cycle whenever CS (RTC chip select) and WE (write enable) are inactive (high) and CE (SRAM chip enable) is active (low). The unique address specified by the 19 address inputs (A0 to A18) defines which of the 524,288 bytes of SRAM data is to be accessed. Valid data will be available to the eight data output drivers within tACC (access time) after the last address input signal is stable, providing that CE and OE (output enable) access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOE for OE rather than address access.
SRAM Write Mode
The DS3050W executes an SRAM write cycle whenever CS is inactive (high) and the CE and WE signals are active (low) after address inputs are stable. The lateroccurring falling edge of CE or WE determines the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The CS and OE control signal should be kept inactive (high) during SRAM write cycles to avoid bus contention. However, if the output drivers have been enabled (CE and OE active) then WE disables the outputs in tODW from its falling edge.
Clock Operations
Table 2. RTC Register Map
ADDRESS xxxxFh xxxxEh xxxxDh xxxxCh xxxxBh xxxxAh xxxx9h xxxx8h xxxx7h xxxx6h xxxx5h xxxx4h xxxx3h xxxx2h xxxx1h xxxx0h X X X X X OSC W WDS AE AM4 AM3 AM2 AM1 Y WF Y AF R BMB4 Y Y Y X X FT X X 10 HOUR 10 MINUTES 10 SECONDS 10 CENTURY BMB3 ABE 10 DATE 10 HOURS 10 MINUTES 10 SECONDS Y 0 Y BLF Y 0 BMB2 Y BMB1 Y Y DATE HOURS MINUTES SECONDS Y 0 Y 0 Y 0 DATA B7 B6 B5 10 YEAR X 10 M 10 DATE X X B4 B3 B2 YEAR MONTH DATE DAY HOUR MINUTES SECONDS CENTURY BMB0 RB1 Y RB0 Y B1 B0 FUNCTION/RANGE YEAR MONTH DATE DAY HOUR MINUTES SECONDS CONTROL WATCHDOG INTERRUPTS ALARM DATE ALARM HOURS ALARM MINUTES ALARM SECONDS UNUSED FLAGS 00-99 01-12 01-31 01-07 00-23 00-59 00-59 00-39 01-31 00-23 00-59 00-59
x = Don't care address bits. X = Unused. Read/writeable under write and read bit control. FT = Frequency test bit. OSC = Oscillator start/stop bit. W = Write bit. R = Read bit. WDS = Watchdog steering bit. BMB0-BMB4 = Watchdog multiplier bits. RB0, RB1 = Watchdog resolution bits. 12
AE = Alarm flag enable. Y = Unused. Read/writeable without write and read bit control. ABE = Alarm in backup mode enable. AM1-AM4 = Alarm mask bits. WF = Watchdog flag. AF = Alarm flag. 0 = Reads as a 0 and cannot be changed. BLF = Battery low flag.
____________________________________________________________________
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock
RTC Read Mode
The DS3050W executes an RTC read cycle whenever CE (SRAM chip enable) and WE (write enable) are inactive (high) and CS (RTC chip select) is active (low). The least significant 4 address inputs (A0 to A3) define which of the 16 RTC registers is to be accessed (see Table 2). Valid data is available to the eight data output drivers within tACC (access time) after the last address input signal is stable, providing that CS and OE (output enable) access times are also satisfied. If CS and OE access times are not satisfied, then data access must be measured from the later occurring signal (CS or OE) and the limiting parameter is either tCO for CS or tOEC for OE rather than address access. External updates are halted by writing a 1 to the read bit (R). As long as a 1 remains in the R bit, updating is inhibited. After a halt is issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command was issued. Normal updates to the external set of registers resume within 1 second after the R bit is set to a 0 for a minimum of 500s. The R bit must be a 0 for a minimum of 500s to ensure the external registers have fully updated.
DS3050W
Setting the Clock
As with a clock read, it is also recommended to halt updates prior to setting new time values. Setting the write bit (W) to a 1 halts updates of the external RTC registers 8h to Fh. After setting the W bit to a 1, the RTC registers can be loaded with the desired count (day, date, and time) in BCD format. Setting the W bit to a 0 then transfers the values written to the internal registers and allows normal clock operation to resume.
RTC Write Mode
The DS3050W executes an RTC write cycle whenever CE is inactive (high) and the CS and WE signals are active (low) after address inputs are stable. The lateroccurring falling edge of CS or WE determines the start of the write cycle. The write cycle is terminated by the earlier rising edge of CS or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t WR) before another cycle can be initiated. The CE and OE control signals should be kept inactive (high) during RTC write cycles to avoid bus contention. However, if the output drivers have been enabled (CS and OE active) then WE disables the outputs in tODW from its falling edge.
Frequency Test Mode
The DS3050W frequency test mode uses the IRQ/FT open-drain output. With the oscillator running, the IRQ/FT output toggles at 512Hz when the FT bit is a 1, the alarm-flag enable bit (AE) is a 0, and the watchdogenable bit (WDS) is a 1 or the WATCHDOG register is written to 00h (FT * AE * (WDS + WATCHDOG)). The IRQ/FT output and the frequency test mode can be used to measure the actual frequency of the 32.768kHz RTC oscillator. The FT bit is reset to a 0 on power-up.
Clock Oscillator Mode
The oscillator can be turned off to minimize battery current drain. The OSC bit is the MSB of the SECONDS register, and must be initialized to a 0 to start the oscillator upon first power application. The OSC bit is factory set to a 1 prior to shipment. Oscillator operation and frequency can be verified by setting the FT bit to a 1 and monitoring the IRQ/FT output for 512Hz.
Using the Clock Alarm
The alarm settings and control for the DS3050W reside within RTC registers 2h-5h. The INTERRUPTS register (6h) contains two alarm-enable bits: alarm enable (AE) and alarm in backup enable (ABE). The AE and ABE bits must be set as described below for the IRQ/FT output to be activated when an alarm match occurs. The alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the DS3050W is in the Data Retention Mode to serve as a system wake-up. Alarm mask bits AM1 to AM4 control the alarm mode (see Table 3). Configurations not listed in the table will default to the once-per-second mode to notify the user of an incorrect alarm setting.
Reading the Clock
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC registers. This puts the external registers into a static state, allowing the data to be read without register values changing during the read process. Normal updates to the internal registers continue while in this state.
____________________________________________________________________
13
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock DS3050W
Table 3. Alarm Mask Bits
AM4 1 1 1 1 0 AM3 1 1 1 0 0 AM2 1 1 0 0 0 AM1 1 0 0 0 0 Once per second When seconds match When minutes and seconds match When hours, minutes, and seconds match When date, hours, minutes, and seconds match ALARM RATE
When the RTC register values match alarm register settings, the alarm flag (AF) is set to a 1. If AE is also a 1, the alarm condition activates the IRQ/FT output. When CS is active, the IRQ/FT signal can be cleared by holding the FLAGS register address stable for tRC and forcing either OE or WE active (see Figure 1). The flag does not change state until the end of the read/write cycle and after the IRQ/FT signal has deasserted. To avoid inadvertently clearing the IRQ/FT signal while preparing for subsequent write/read cycles at other register addresses, assure that tAW is met for that subsequent address (see Figure 2).
The IRQ/FT output can also be activated during battery backup mode. The IRQ/FT goes low if an alarm occurs and both AE and ABE are set to 1. The AE and ABE bits are reset to 0 during the power-up transition, but an alarm generated during power-up will set AF to a 1. Therefore, the AF bit can be read after system powerup to determine if an alarm was generated during the power-up sequence. Figure 3 illustrates alarm timing during battery backup mode and power-up states.
CE
WE OR OE
CS
tRC MAX ADDRESS 0h
A0-A3
IRQ/FT
HIGH IMPEDANCE
Figure 1. Clearing Active IRQ Waveforms
14
____________________________________________________________________
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock DS3050W
CE
tAS WE OR OE INADVERTENT WRITE OR READ OF RTC FLAGS REGISTER WILL RESET IRQ/FT INTENTIONAL WRITE OR READ AT ADDRESS Xh
CS
A0-A3
ADDRESS 0h
ADDRESS Xh
IRQ/FT
HIGH IMPEDANCE
Figure 2. Prevent Accidental Clearing of IRQ Waveforms
VTP VCC
ABE, AE
AF
IRQ/FT
HIGH IMPEDANCE
HIGH IMPEDANCE
Figure 3. Battery Backup Mode Alarm Waveforms
____________________________________________________________________
15
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock DS3050W
Using the Watchdog Timer
The watchdog timer can be used to detect an out-ofcontrol processor. The user programs the watchdog timer by setting the desired timeout delay into the WATCHDOG register. The five high-order WATCHDOG register bits store a binary multiplier and the two lowerorder WATCHDOG bits select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The watchdog timeout value is then determined by multiplication of the 5-bit multiplier value with the 2-bit resolution value. (For example: writing 00001110 (0Eh) into the WATCHDOG register = 3 x 1 second, or 3 seconds.) If the processor does not reset the timer within the specified period, the watchdog flag (WF) is set to a 1 and a processor interrupt is generated and stays active until either WF is read or the WATCHDOG register is read or written. The MSB of the WATCHDOG register is the watchdog steering bit (WDS). When WDS is set to a 0, the watchdog activates the IRQ/FT output when the watchdog times out. WDS should not be written to a 1, and should be initialized to a 0 if the watchdog function is enabled. The watchdog timer resets when the processor performs a read or write of the WATCHDOG register. The timeout period then starts over. The watchdog timer is disabled by writing a value of 00h to the WATCHDOG register. The watchdog function is automatically disabled upon power-up and the WATCHDOG register is cleared to 00h. energy source. Normal clock or SRAM operation can resume after VCC exceeds VTP for a minimum duration of tREC.
Battery Charging
When VCC is greater than VTP an internal regulator will charge the battery. The UL-approved charger circuit includes short-circuit protection and a temperature-stabilized voltage reference for on-demand charging of the internal battery. Typical data retention expectations greater than 2 years per charge cycle are achievable. A maximum of 96 hours of charging time is required to fully charge a depleted battery.
System Power Monitoring
When the external VCC supply falls below the selected out-of-tolerance trip point, the output RST is forced active (low). Once active, the RST is held active until the VCC supply has fallen below that of the internal battery. On power-up, the RST output is held active until the external supply is greater than the selected trip point and one reset timeout period (tRPU) has elapsed. This is sufficiently longer than tREC to ensure that the RTC and SRAM are ready for access by the microprocessor.
Freshness Seal and Shipping
The DS3050W is shipped from Dallas Semiconductor with the RTC oscillator disabled and the lithium battery electrically disconnected, guaranteeing that no battery capacity has been consumed during transit or storage. As shipped, the lithium battery is ~60% charged, and no pre-assembly charging operations should be attempted. When VCC is first applied at a level greater than VTP, the lithium battery is enabled for backup operation. The user is required to enable the oscillator (MSB of SECONDS register) and initialize the required RTC registers for proper timekeeping operation. A 96 hour initial battery charge time is recommended for new system installations.
Power-On Default States
Upon each application of power to the device, the following register bits are automatically set to 0: WDS = 0, BMB0-BMB4 = 0, RB0, RB1 = 0, AE = 0, ABE = 0. All other RTC bits are undefined.
Data-Retention Mode
The DS3050W provides full functional capability for VCC greater than 3.0V and write-protects by 2.8V. Data is maintained in the absence of VCC without additional support circuitry. The NV SRAM constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write-protects itself. All inputs become don't care, and all data outputs become high impedance. As VCC falls below approximately 2.5V (VSW), the power-switching circuit connects the lithium energy source to the clock and SRAM to maintain time and retain data. During power-up, when VCC rises above VSW, the power-switching circuit connects external VCC to the clock and SRAM, and disconnects the lithium
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS3050W, assure that all VCC and GND balls are connected and decouple the power supply with a 0.1F capacitor. Use a high-quality, ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications.
16
____________________________________________________________________
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock
Avoiding Data Bus Contention
Care should be taken to avoid simultaneous access of the SRAM and RTC devices (see Figure 4). Any chipenable overlap violates tCCS and can result in invalid and unpredictable behavior.
DS3050W
Recommended Reflow Temperature Profile
PROFILE FEATURE Average Ramp-Up Rate (TL to TP) Preheat - Temperature Min (TSmin) - Temperature Max (TSmax) - Time (Min to Max) (ts) TSmax to TL - Ramp-Up Rate Time maintained above: - Temperature (TL) - Time (tL) Peak Temperature (TP) Time Within 5C of Actual Peak Temperature (TP) Ramp-Down Rate Time 25C to Peak Temperature +183C 60 to 150 Seconds 225 +0/-5C 10 to 30 Seconds 6C/Second Max 6 Minutes Max Sn-Pb EUTECTIC ASSEMBLY 3C/Second Max
Using the Open-Drain IRQ/FT and RST Outputs
The IRQ/FT and RST outputs are open drain, and therefore require pullup resistors to realize a high logic output level. Pullup resistor values between 1k and 10k are typical.
100C 150C 60 to 120 Seconds
Battery Charging/Lifetime
The DS3050W charges an ML battery to maximum capacity in approximately 96 hours of operation when VCC is greater than VTP. Once the battery is charged, its lifetime depends primarily on the VCC duty cycle. The DS3050W can maintain data from a single, initial charge for up to 2 years. Once recharged, this deepdischarge cycle can be repeated for up to 20 times, producing a worst-case service life of 40 years. More typical duty cycles are of shorter duration, enabling the DS3050W to be charged hundreds of times, and extending the service life well beyond 40 years.
Recommended Cleaning Procedures
The DS3050W can be cleaned using aqueous-based cleaning solutions. No special precautions are needed when cleaning boards containing a DS3050W module. Removal of the topside label violates the environmental integrity of the package and voids the warranty of the product.
Note: All temperatures refer to topside of the package, measured on the package body surface.
VIH CE tCCS tCCS
VIH
VIH CS
VIH
Figure 4. SRAM/RTC Data Bus Control
____________________________________________________________________
17
3.3V Single-Piece 4Mb Nonvolatile SRAM with Clock DS3050W
Pin Configuration
TOP VIEW
A B C D E F G H J K L M N P R T U V W Y 1 1 2 GND N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VCC IRQ/FT A15 A16 RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND CS GND GND 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 GND A18 A17 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 N.C. N.C. GND GND 1 9 2 0 2 0 A B C D E F G H J K L M N P R T U V W Y
DS3050W
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) DS3050W BGA modules are recognized by Underwriters Laboratory (UL) under file E99151.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.

▲Up To Search▲

Price & Availability of DS3050W

	To Download DS3050W Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .